The present invention generally relates to memory cards, and more particularly to a memory card which has a memory function and has a shape of a credit card, for example.
There has been proposed a memory card which has no central processing unit (CPU) but has a built-in memory such as a random access memory (RAM) and a read only memory (ROM). For example, the memory card uses a data bus having a bit width of eight bits or sixteen bits, and there are proposals to use a data bus having a bit width which is a multiple of eight such as thirty-two bits and sixty-four bits. When such a memory card is loaded into a card write and/or read apparatus (hereinafter simply referred to as a card write/read apparatus), it is possible to write arbitrary information to the memory card and/or read prestored information from the memory card.
FIG. 1 shows an example of a conventional memory card. The memory card comprises an input buffer 100, a memory 101, an input/output buffer 102, and terminals 103 through 107. An address signal ADR is applied to the terminal 103, a write enable signal WE is applied to the terminal 104, a chip select signal CS is applied to the terminal 105, and an output enable signal OE is applied to the terminal 106. A write datum which is to be written into the memory 101 and a read datum which is read out from the memory 101 are input and output via the data input/output terminal 107. The input of the write datum is controlled by the input/output buffer 102 in response to the write enable signal WE. On the other hand, the output of the read datum is controlled by the input/output buffer 102 in response to the output enable signal OE.
According to the conventional memory card, the bit width of the data input/output terminal 107, that is, the bit width of a data bus, determines the card write/read apparatus to which the memory card may be loaded. In other words, a memory card which has a data bus with a bit width of eight bits is used exclusively on a card write/read apparatus having a data bus with a bit width of eight bits. Similarly, a memory card which has a data bus with a bit width of sixteen bits is used exclusively on a card write/read apparatus having a data bus with a bit width of sixteen bits. For this reason, when the bit width of the data bus of the card write/read apparatus is changed from eight bits to sixteen bits, it no longer becomes possible to use the memory card which has the data bus with the bit width of eight bits and the memory cards used on this card write/read apparatus must all have the data bus with the bit width of sixteen bits. As a result, an extremely large scale modification must be made in order to extend the functions of the card write/read apparatus because it is necessary to change all the memory cards.
Therefore, the bit width of the data bus of the card write/read apparatus conventionally determines the memory cards which may be used thereon. Thus, there is a problem in that a memory card which has a data bus with a bit width different from that of the card write/read apparatus cannot be used on this card write/read apparatus.
It is possible to consider enabling compatible use of the memory card which has the data bus with the bit width of sixteen bits on the card write/read apparatus which has the data bus with the bit width of eight bits and the card write/read apparatus which has the data bus with the bit width of sixteen bits. In this case, if the memory cards used have the data bus with the bit width of sixteen bits to start with, it is possible to continue using these memory cards even when the bit width of the data bus of the card write/read apparatus is changed from eight bits to sixteen bits to extend the functions thereof.
FIG. 2 shows another example of the conventional memory card. In FIG. 2, those parts which are substantially the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. The memory card shown in FIG. 2 has a data bus with a bit width of sixteen bits. The memory card comprises two 256 k.times.8 bit RAMs 101.sub.L and 101.sub.H, a terminal 105.sub.L for receiving a chip select signal CS0 which selects a lower byte (that is, the RAM 101.sub.H), and a terminal 105.sub.H for receiving a chip select signal CS1 which selects an upper byte (that is, the RAM 101.sub.H). The following Table 1 shows an operation mode of the memory card determined by the chip select signals CS0 and CS1, where "H" denotes a high logic level and "L" denotes a low logic level.
TABLE 1 ______________________________________ CS1 CS0 Operation Mode ______________________________________ H H Non-Select H L Lower Byte Select L H Upper Byte Select L L Word Access ______________________________________
When the memory card shown in FIG. 2 is used on the card write/read apparatus having the data bus with the bit width of eight bits, it is necessary to generate the chip select signals CS0 and CS1 by providing a decoder circuit within the card write/read apparatus because the card write/read apparatus having the data bus with the bit width of eight bits originally does not have the function of generating the chip select signals CS0 and CS1. Accordingly, in this case, there is a problem in that the card write/read apparatus having the data bus with the bit width of eight bits must be redesigned extensively to incorporate the decoder circuit by taking into account a signal delay which occurs within the decoder circuit. Further, after such a redesigning is made, it no longer is possible to use the memory card which has the data bus with the bit width of eight bits.